As the frequency of external interfaces in computer systems increases and the channel improvement continues to be modest while maintaining back-ward compatibility, the need to use retimers in interfaces has increased. For example, Peripheral Component Interface Express (PCIe) Generation 4, in which the interface operates at 16.0 GT/s, will need a retimer for most server channels which are typically 20″ FR4 with two connectors. Universal Serial Bus (USB) Version 3.1 operates at 10 GT/s and already needs a retimer for most platforms. Other interfaces needs some form of extension device for some of platforms that operate at 10.4 GT/s.
There are multiple challenges with each of these interfaces. For cache-coherency protocols such as Ultra Path Interconnect (UPI), an additional latency of about 30 nsec per retimer hop makes it untenable due to the unacceptable performance loss. Latency is already an issue even with PCIe for some memory applications and is expected to become more serious as the next-generation non-volatile memory (NVM) technologies provide higher bandwidth and lower latency, closing the gap with double data rate synchronous dynamic random-access memory (DDR SDRAM). An analog re-driver does not have the latency issue. However, since it does not participate in the link initialization and equalization phase, the analog re-driver fails to recreate the transmitter equalization space, unlike the re-timers, and hence will have limited use, especially with open slots/connectors type systems.
A second challenge is multiple protocol support through different physical layers (PHYs) as there are in a Type-C connector. Having a separate retimer with a physical multiplexer to separate between the different PHYs may be a possible solution, but is expensive and can take up valuable board real-estate along with increased power.
A third challenge is the number of different retimers have to be supported in certain platforms and the associated validation and impose inter-operability challenges.